A Methodology for Synthesis of Data Path Circuitse

tioned into data path and control blocks. The data path block performs Boolean (AND, OR, XOR) or arithmetic (ADD, SHIFT, MULTIPLY) operations on data and address buses. Control logic generates signals that control the data path’s operation. Control logic is usually very random, whereas data path logic is highly regular because it performs similar operations on different bits of the same bus. Designers exploit this regularity to achieve regular layouts with small areas and high performance. Furthermore, data path regularity defines a natural hierarchy that improves design productivity by speeding up incremental changes and reducing layout effort. Thus, a key step in data path circuit design is to identify and preserve the inherent regularity. Existing circuit synthesis tools target the design of random control logic. They neither identify nor preserve regularity during the synthesis process and therefore are unsuitable for data path circuit design. (The “Previous work” sidebar briefly reviews earlier data path synthesis methodologies.) Lacking synthesis tools for data paths, microprocessor designers often design the entire data path manually.1 Consequently, data path circuit design takes considerable time and effort in the design cycle of a high-performance microprocessor. The increasing size and complexity of VLSI processors make automated synthesis of data path logic crucial to meeting design productivity goals. We have developed a new methodology for fast, efficient synthesis of data path circuits. Our methodology automates various steps in the design process yet allows the designer to control the overall process. The methodology has several features unique to data path synthesis. First, it includes algorithms that extract and preserve regularity during the synthesis process,2 unlike existing circuit synthesis techniques, which largely ignore data path regularity. Second, our methodology efficiently incorporates floorplanning information for data path blocks and uses the resulting accurate interconnect-parasitic information to drive the gatesizing algorithms for data path circuits. This feature is significant: Unlike random logic, data path circuits can have large interconnect parasitics because some signals cross buses up to 64 bits wide. Incorporating the layout parasitics during circuit synthesis drastically reduces the time spent alternating between the circuit and layout design steps—an extremely timeconsuming task in manual design. Finally, our synthesis methodology allows the use of a wide range of circuit technologies, such as the static CMOS, domino, pass-gate, and tristate-gate technologies. This makes our approach A Methodology for Synthesis of Data Path Circuits Data Path Synthesis